Field of the Invention
The present invention relates to a comparator for a wide supply voltage range, in which a source follower is connected downstream of a differential amplifier stage, and a switch closes a feedback loop from the source follower to the differential amplifier stage.
A known use of comparators in electronics is for decoding whether a voltage is larger or smaller than a comparative voltage. Thus, for example, A/D converters based on the principle of successive approximation use multistage comparators as shown schematically in FIG. 2 in which comparator stages 1 are connected in series via capacitors 2. During a sample phase, feedback switches 3, which bridge the individual comparator stages 1, are closed while an input voltage uin is applied to an input 4. The offset value for the individual comparator stages 1 and the voltage uin to be measured are stored in the capacitors 2. In the course of such operation, each individual stage sets its own operating point, while the gain has the value zero because the comparators are bridged by means of the switches 3.
At a sample instant, all the feedback switches 3 are then opened and a comparative voltage ref is added to the input 4. Each comparator stage 1 thus amplifies the difference between the voltages uin and ref by a factor of approximately 10. By this means, a small difference at the input 4 encounters a voltage level which can be processed by a downstream logic configuration at an output 5 of the last comparator stage 1.
Such multistage comparators are described, for example, in IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 6, Dec. 7, 1982; Vol. 27, No. 12, December 1992; and in European patent 0407859 B1.
The individual stages of the comparator shown in FIG. 2 have hitherto been designed as a differential amplifier stage with a downstream source follower, as shown in FIG. 3. Thus, in FIG. 3 a differential amplifier stage 6 is connected at the input and the output to a source follower 7. In such a circuit configuration, it has been shown that the current which is mirrored in at a reference ground point 8 of the differential amplifier 6 is about 20% larger than the sum of the currents which are impressed by two upper current sources 9. The remaining 20% of the current is taken by two PMOS diodes 10.
The structure of the circuit configuration of in FIG. 3 was developed from a simple differential stage, as shown in FIG. 4.
The problem of such a differential amplifier is the switches 3 which are used to close a feedback loop for the differential amplifier 6.
The reason for this is that in A/D converters operating on the principle of successive approximation--explained above with reference to FIG. 2--it has to be assumed that a positive or negative voltage step change of at least half the comparative voltage ref can occur during the conversion at the input of a comparator stage 1. With an input voltage uin of VDD=5 V and a comparative voltage ref where Vref=5 V, the comparator must be able to process a step change of 2.5 V at the input 4. In the case of the differential amplifier 6, the operating point of a node a1 or a node q1 after offset adjustment is at approximately 3.8 V, that is to say the difference between the voltage VDD and the threshold voltage of the PMOS diode 10. That operating point is held firmly by the PMOS diode 10.
If a PMOS transistor is used for the switch 3, a positive voltage step change at the input 4 then becomes the problem because the diodes 100 at the source and drain of the transistor (switch 3) are turned on, as shown schematically in FIG. 5. Consequently, charge flows away from a node e1 after the positive or negative voltage step change until the potential at the node e1 is smaller than the sum of the voltage VDD and the diode forward voltage. Subsequent comparator decisions therefore become incorrect with successive approximation, so that the conversion result is no longer correct either.
If an NMOS transistor is used for the switch 3, this problem of a voltage step change does not occur because the diodes 100 can become active only toward ground voltage VSS. This, however, in turn causes problems with a substrate control effect of the NMOS transistor used as the switch 3.
In such a circuit shown in FIG. 6, the semiconductor body (bulk) of the switch 3 is at ground voltage VSS, while the source and drain have the difference between the voltage VDD and a threshold value voltage Vth applied to them. Under these conditions, the switch 3 has a high impedance even if 5 V is applied to its gate terminal.
In order then to solve these switch problems, the source follower 7 has hitherto been connected downstream of the differential amplifier 6, and the sample phase has been fed back via the two stages, that is to say the differential amplifier 6 and the source follower 7. As a result of this source follower 7, the operating point at the node e1 and/or e1q is lower than the voltage at the node a1 and/or at the node q1 by the threshold value voltage Vth.
It follows that, if the comparator is to operate satisfactorily within a wide supply voltage range, there is little use for a circuit configuration with a downstream source follower 7.
In an A/D converter for a cordless telephone (DECT system), battery operation may cause the operating voltage VDD to fluctuate between 2.8 V and 5.4 V. The solution using a downstream source follower 7 cannot be applied satisfactorily here, since the PMOS diode 10, the source follower and the input transistors of the differential amplifier 6 mean that three transistors are connected between the voltage VDD and the voltage VSS, as shown in FIG. 7.
With the threshold voltages of approx. 1 V provided by this technology for the individual transistors, as much as 3 V overall are thus required for these transistors. Furthermore, an additional 0.5 V or so for the current source at the reference ground point 8 of the differential amplifier 6 should be available. It is therefore not possible to operate such a comparator at a supply voltage of about 2.8 V.